AGP SBA question

I've been looking over the AGP 3.0 spec. and noticed there appear to be 8
pins dedicated to SBA and that SBA is a one way bus (from vid card to AGP
port). This is about all I was able to get out of the documentation though.

Is SBA merely the method by which a video card xfers addresses in the AGP
aperture range for which it will read/write? Are these addresses 32-bits in
length? If they are 32-bits how do the 8 SBA pins xfer these 32-bits? Is it
some sort of DDR scheme?

--
Doug

On Tue, 14 Nov 2006 18:39:27 GMT, "pigdos" <NA.TakeThisOut@nowhere.com> wrote:

>I've been looking over the AGP 3.0 spec. and noticed there appear to be 8
>pins dedicated to SBA and that SBA is a one way bus (from vid card to AGP
>port). This is about all I was able to get out of the documentation though.

It's one-way because address requests to main memory only go in the one
direction, from the AGP device to the chipset.

>Is SBA merely the method by which a video card xfers addresses in the AGP
>aperture range for which it will read/write? Are these addresses 32-bits in
>length? If they are 32-bits how do the 8 SBA pins xfer these 32-bits? Is it
>some sort of DDR scheme?

SBA == Side Band Addressing. Note that AGP 3.0 dropped pipelined
addressing on the multiplexed Address/Data Bus. The AGP address
transactions are not just 32-bit addresses - since an AGP data transfer is
8 bytes min-length/aligned, the bottom 3 bits are used for transaction
length info. There's also command info which is transferred on the four
C/BE pins for the non-SBA multiplexed transactions on the Address/Data Bus.

When SBA is used, the C/BE pins are not used for the 4-bit command request
code which is folded into the SBA transaction request, which can handle a
36-bit memory address and also includes the length info and the SBA command
"type code", so that a full SBA transaction can be up to 48-bits in length
and require six SBA bus transfers... *BUT* there are also sticky bits for
addresses, which are held in the target (chipset) from a previous
transaction, so that if an address differs only in the bottom 15 bits from
that of the previous transaction, only 2 bus transfers are required.

There is also an optional extended mode SBA command type which allows for
48-bit memory addresses but I guess that's become kinda academic now with
PCI-E taking over.

The SBA Bus runs at the same 8x speed as the data bus, i.e. clocked at 4x
the base clock plus DDR.

The AGP 2.0 docs cover some of this better than the AGP 3.0, which is
written, in some places, as a comparison with the previous spec.

--
Rgds, George Macdonald