Jethro wrote:
> I'm confused as usual.
>
> I read of L1 and L2 caches in CPU specs,
> DDRs are memory cards added to the MOBO.
> I read of FSB in MOBO specs.
>
> So if the caches are integral to the CPU, and DDr provides added
> memory, where is the FSB? On the MOBO?
>
> Thanks
>
> Jethro
It is all very confusing, and the details differ between
major families. The answer is a little different, when
comparing Athlon64 say, to a current Core2 Duo or a P4 or
even an AthlonXP. The Athlon64 uses different design principles,
that make "FSB" a more fuzzy terminology.
Loosely speaking, every storage system in your computer, can
be viewed as a level of cache. L1 and L2 currently, tend to be
full speed caches - they have multi-cycle latency (delay) to
get your data, but the clock speed of the memory can be
equivalent to the speed of the core they are connected to.
Your computer main memory is really slow by comparison, and
might be referred to as an "L3" or "Level3" cache. Your hard
drive might be considered to be the "L4" or "Level4" cache
fot the system.
On an old P4 processor, the major blocks in the system look like this.
The Front Side Bus (FSB) is physical and is right on the pins
of the processor.
--------
| Core | An old FSB800 speed Pentium4 processor
| L1 |
| L2 |
--------
|
FSB | 64 bits at 800MHz or 6.4GB/sec (800MHz is quad pumped)
| Processor clock 200MHz x 4 establishes transfer rate
PCIe |
Video <--> Northbridge <---> Memory DIMMs
x16 |
| Hub bus, perhaps 1GB/sec. Differs per chipset/generation.
|
Southbridge <---> Disk drives, USB, maybe LAN etc
|
SuperIO <---> Floppy, Serial, Parallel Port
On an Athlon64, the design looks more like this. Note that
I am not providing any details about the exact arrangement of
Core, L1, L2 (cause I'm lazy). They're just blocks for this discussion.
--------------------
| Core | Athlon64
| L1 |
| L2 |
| |
| |
| Memory_Controller |<---> Memory DIMMs
| |
--------------------
|
| Hypertransport - two sets of serial, packet oriented
| lanes, operating at 2000MHz or so.
| - (200MHz x 5) x 2 (DDR) gives data rate
| - 16 bit bus, each direction
| - 4GB/sec up, 4GB/sec down (same as PCIe x16)
PCIe |
Video <--> Northbridge
x16 |
| Hypertransport - may be narrower than the main bus
|
Southbridge <---> Disk drives, USB, maybe LAN etc
|
SuperIO <---> Floppy, Serial, Parallel Port
Now, in all the excitement, what is missing from the second diagram ?
The FSB
You might consider the FSB to be just before the Memory
Controller, in order to compare "Intel" to "AMD". Or instead of
working virtually, you might try to label the diagram physically -
the FSB might be viewed as the upper Hypertransport bus.
http://en.wikipedia.org/wiki/Athlon64
"...there is no FSB for the system memory to base its speed upon"
But the busses are quite dissimilar in terms of implementation.
Hypertransport is kinda like Ethernet, and uses packets. It is a
narrow bus, running at high speed. Its least efficient mode, might
be transferring small data items, due to the packet overhead (address,
CRC checks, stuff like that). When it transfers bursts of data (for
say the video card), it is much more efficient, as a longer packet
can be used.
The Intel FSB is a parallel bus, as far as I know. I don't know how
the address and data rates compare, whether they are 1:1 or some
other ratio. (On the AthlonXP for example, I think presentation
of addresses happens at a slower rate than data. AthlonXP uses
a split transaction bus, decoupling address and data. The AMD762
datasheet is as close as I can get to details about that bus.)
All good fun stuff.
Paul
>> Stay informed about: Cache vs FSB vs DDR memory? 
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