Questions about DDR RAM

In article <YI%Pi.6038$lE2.4625@newssvr22.news.prodigy.net>,
redelm.DeleteThis@ev1.net.invalid says...

> "Beware of programmers who carry screwdrivers" [Leonard Brandwein]

At the PPOE, the software types got nervous when the hardware types
came around with screwdrivers too. Once, after assuring them that we
really did know what we were doing, we installed a crypto feature on
their test vehicle. Bringing up the hardware (the second copy in
existence) we found a signal didn't get "from here to there". So we
powered off the system before removing the logic modules (about 4"
water-cooled cubes) trying to track down the errant signal. When we
disconnected the water jacket it all of a sudden got very quiet and
programmers started coming out of the woodwork to see what happened.
The dumb bastards had switched the consoles from one side of the MP
configuration to the other so we were trying to debug the hardware on
one side with the console on the other. No wonder the signal didn't
get from here to there. Those things (1200W logic modules) sure
didn't appreciate running without water either.

--
Keith
 >> Stay informed about: Questions about DDR RAM 

Frank McCoy wrote:

>>>OK ... That actually makes sense.
>>>Still, there *are* several extra chips on the ECC-capable DIMM.
>>>Extra data requires extra places to store it.
>>
>>What part of "There is absolutely no logic on the DIMMs that contribute to ECC
>>- other than the extra drams for storage of the ECC check bits." did you miss?
>>
>The "other than the extra dram" part.

Which is one extra chip, not "several".
 >> Stay informed about: Questions about DDR RAM 

In article <ofs6h3dtim49no0dpik5mr6tdn12p8jue9.DeleteThis@4ax.com>,
chrisv.DeleteThis@nospam.invalid says...
> Frank McCoy wrote:
>
> >>>OK ... That actually makes sense.
> >>>Still, there *are* several extra chips on the ECC-capable DIMM.
> >>>Extra data requires extra places to store it.
> >>
> >>What part of "There is absolutely no logic on the DIMMs that contribute to ECC
> >>- other than the extra drams for storage of the ECC check bits." did you miss?
> >>
> >The "other than the extra dram" part.
>
> Which is one extra chip, not "several".

The address bus and control signals go to all of the chips.

--
Keith
 >> Stay informed about: Questions about DDR RAM 

In alt.comp.hardware.pc-homebuilt chrisv <chrisv RemoveThis @nospam.invalid> wrote:

>Frank McCoy wrote:
>
>>>>OK ... That actually makes sense.
>>>>Still, there *are* several extra chips on the ECC-capable DIMM.
>>>>Extra data requires extra places to store it.
>>>
>>>What part of "There is absolutely no logic on the DIMMs that contribute to ECC
>>>- other than the extra drams for storage of the ECC check bits." did you miss?
>>>
>>The "other than the extra dram" part.
>
>Which is one extra chip, not "several".

How do you get several more bits with only one chip?
This isn't parity, but ECC.

As I recall a SECDED hamming-code for 32-bits would require a minimum of
7 extra bits for single-bit ECC correction and double-bit parity-error
detection.

If a standard DIMM gets 4 bits each in 8 chips, that would require a
minimum of two more chips, not one.

--
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 >> Stay informed about: Questions about DDR RAM 

Frank McCoy wrote:
> How do you get several more bits with only one chip?
> This isn't parity, but ECC.
>
> As I recall a SECDED hamming-code for 32-bits would require a minimum of
> 7 extra bits for single-bit ECC correction and double-bit parity-error
> detection.
>
> If a standard DIMM gets 4 bits each in 8 chips, that would require a
> minimum of two more chips, not one.
>

First of at it's not 32 bits. And 8 bits per 64 works well

rgds
\SK
 >> Stay informed about: Questions about DDR RAM 

In article <j7i8h31qudb0vkkkela1acqdsjriuoi4oi.DeleteThis@4ax.com>,
mccoyf.DeleteThis@millcomm.com says...
> In alt.comp.hardware.pc-homebuilt chrisv <chrisv.DeleteThis@nospam.invalid> wrote:
>
> >Frank McCoy wrote:
> >
> >>>>OK ... That actually makes sense.
> >>>>Still, there *are* several extra chips on the ECC-capable DIMM.
> >>>>Extra data requires extra places to store it.
> >>>
> >>>What part of "There is absolutely no logic on the DIMMs that contribute to ECC
> >>>- other than the extra drams for storage of the ECC check bits." did you miss?
> >>>
> >>The "other than the extra dram" part.
> >
> >Which is one extra chip, not "several".
>
> How do you get several more bits with only one chip?

Chips, these days, are more than one bit wide. X-1 chips went out
with button shoes.

> This isn't parity, but ECC.

The memory doesn't know the difference.

> As I recall a SECDED hamming-code for 32-bits would require a minimum of
> 7 extra bits for single-bit ECC correction and double-bit parity-error
> detection.

Memory is 64bits wide these days. Run your numbers again.

> If a standard DIMM gets 4 bits each in 8 chips, that would require a
> minimum of two more chips, not one.

Try 8bits each in eight chips, add a ninth for parity/ECC.

--
Keith
 >> Stay informed about: Questions about DDR RAM 

In comp.sys.ibm.pc.hardware.chips krw <krw.TakeThisOut@att.bizzzz> wrote:
> Memory is 64bits wide these days. Run your numbers again.

Quibble: *DIMMs* are 64-bits wide these days.

Memory, even just talking about main memory on the PC architecture, runs
from 64 bits to 256 (possibly 512, if you count AMD's lightweight NUMA as
parallel. Otherwise, 256 is for the quad-channel Xeon boards.)

ISTR some fairly ridiculous bus widths for high-end graphics cards, as well.

--
Nate Edel http://www.cubiclehermit.com/
preferred email | "With all the accumulated wit and wisdom in the
is "nate" at the | world, it is pointless to try to select a few
posting domain | choice quotes." (some guy from my HS yearbook)
 >> Stay informed about: Questions about DDR RAM 

In article <2v6gu4xld9.ln2.RemoveThis@mail.sfchat.org>, archmage.RemoveThis@sfchat.org
says...
> In comp.sys.ibm.pc.hardware.chips krw <krw.RemoveThis@att.bizzzz> wrote:
> > Memory is 64bits wide these days. Run your numbers again.
>
> Quibble: *DIMMs* are 64-bits wide these days.

We were talking about memory.

> Memory, even just talking about main memory on the PC architecture, runs
> from 64 bits to 256 (possibly 512, if you count AMD's lightweight NUMA as
> parallel. Otherwise, 256 is for the quad-channel Xeon boards.)

We were talking about memory, not processor implementation. Do you
have an example of an x86 processor with a wider than 64bit data path
to the DIMM (ignoring dual channel for the moment, which is simply
two DIMMs)?

> ISTR some fairly ridiculous bus widths for high-end graphics cards, as well.

We were... Do you really have parity/ECC on graphics cards?

--
Keith
 >> Stay informed about: Questions about DDR RAM 

On 2007-10-16, Frank McCoy <mccoyf DeleteThis @millcomm.com> wrote:
>
> How do you get several more bits with only one chip?
> This isn't parity, but ECC.
>
> As I recall a SECDED hamming-code for 32-bits would require a minimum of
> 7 extra bits for single-bit ECC correction and double-bit parity-error
> detection.

Only a standard DIMM is a 64 bit module, not 32. An additional
bit is required due to the enlarged module word size and so ECC
DIMM is 72 bit to accommodate the extra data. Taking a standard
8-chip DIMM you see that each chips takes 8 bit words and so only
a single additional module is required.

--
Andrew Smallshaw
andrews DeleteThis @sdf.lonestar.org
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In comp.sys.ibm.pc.hardware.chips krw <krw.RemoveThis@att.bizzzz> wrote:
> In article <2v6gu4xld9.ln2.RemoveThis@mail.sfchat.org>, archmage.RemoveThis@sfchat.org
> says...
> > In comp.sys.ibm.pc.hardware.chips krw <krw.RemoveThis@att.bizzzz> wrote:
> > > Memory is 64bits wide these days. Run your numbers again.
> >
> > Quibble: *DIMMs* are 64-bits wide these days.
>
> We were talking about memory.

Yes; all DIMMs are memory, but not all memory comes in DIMMs.

Memory comes in lots of widths, and no more explicitly applies to DIMMs than
to the individual chips on the DIMMs or soldered to a board.

> > Memory, even just talking about main memory on the PC architecture, runs
> > from 64 bits to 256 (possibly 512, if you count AMD's lightweight NUMA as
> > parallel. Otherwise, 256 is for the quad-channel Xeon boards.)
>
> We were talking about memory, not processor implementation. Do you
> have an example of an x86 processor with a wider than 64bit data path
> to the DIMM (ignoring dual channel for the moment, which is simply
> two DIMMs)?

x86? No, although you're changing the goalposts, and I did say it was a
quibble. The AMD dual channel implementation *IS* a full 128-bit path to
memory, just split between two DIMMs.

I have no idea what IBM uses for memory in their very high-end stuff, but
that's not x86; even high-end stuff from Sun, etc, tends to just use
multiple channels breaking down to DIMMs.

> > ISTR some fairly ridiculous bus widths for high-end graphics cards, as well.
>
> We were... Do you really have parity/ECC on graphics cards?

Not on consumer stuff.

It's been a *long* time since I've paid attention to high-end workstation
graphics boards. It would be pretty implausible on consumer stuff or on
today's "derived from consumer" FireGL or Quadro boards.

Anyone have an old IBM PGA board from the mid-80s? I'd be quite surprised if
that DIDN'T have parity.

--
Nate Edel http://www.cubiclehermit.com/
preferred email | "With all the accumulated wit and wisdom in the
is "nate" at the | world, it is pointless to try to select a few
posting domain | choice quotes." (some guy from my HS yearbook)
 >> Stay informed about: Questions about DDR RAM 

On Thu, 18 Oct 2007 14:50:15 -0700, archmage.DeleteThis@sfchat.org (Nate Edel) wrote:
[...]
>Anyone have an old IBM PGA board from the mid-80s? I'd be quite surprised if
>that DIDN'T have parity.

Really?
Why would *anyone* actually want parity on graphics memory?

/daytripper
(who's been surprised before...but I don't think it's happening this time
 >> Stay informed about: Questions about DDR RAM 

In comp.sys.ibm.pc.hardware.chips daytripper <day_trippr RemoveThis @removeyahoo.com> wrote:
> On Thu, 18 Oct 2007 14:50:15 -0700, archmage RemoveThis @sfchat.org (Nate Edel) wrote:
> [...]
> >Anyone have an old IBM PGA board from the mid-80s? I'd be quite surprised if
> >that DIDN'T have parity.
>
> Really?
> Why would *anyone* actually want parity on graphics memory?

Framebuffer? Probably doesn't matter, since it's being rewritten
continuously.

That said, there's more to graphics memory ... and for some apps, you could
well want ECC any time the graphics memory contains uploadable code.

I was under the impression modern 3D stuff does, but it may always get the
instruction stream pushed to it? See also attempts to use the GPU as a
general vector processor for non-video use.

That said...

According to Wikipedia, what I was thinking of was the "PGC" (Professional
Graphics Controller) not the PGA, here's the article.

http://en.wikipedia.org/wiki/Professional_Graphics_Controller

It was a big ol' nightmare of a card, and basically a CAD accelerator. It
had its own memory and processor. That said, the picture here looks like
it's got banks of 8 chips: http://www.seasip.info/VintagePC/pgc.html so I
am probably wrong in my guess.

I've got a couple of old DEC systems with framebuffer cards, and could dig
those out, but they're relatively low-end early 1990s ones.

--
Nate Edel http://www.cubiclehermit.com/
preferred email | "With all the accumulated wit and wisdom in the
is "nate" at the | world, it is pointless to try to select a few
posting domain | choice quotes." (some guy from my HS yearbook)
 >> Stay informed about: Questions about DDR RAM 

In alt.comp.hardware.pc-homebuilt archmage RemoveThis @sfchat.org (Nate Edel) wrote:

>In comp.sys.ibm.pc.hardware.chips krw <krw RemoveThis @att.bizzzz> wrote:
>> In article <2v6gu4xld9.ln2 RemoveThis @mail.sfchat.org>, archmage RemoveThis @sfchat.org
>> says...
>> > In comp.sys.ibm.pc.hardware.chips krw <krw RemoveThis @att.bizzzz> wrote:
>> > > Memory is 64bits wide these days. Run your numbers again.
>> >
>> > Quibble: *DIMMs* are 64-bits wide these days.
>>
>> We were talking about memory.
>
>Yes; all DIMMs are memory, but not all memory comes in DIMMs.
>
>Memory comes in lots of widths, and no more explicitly applies to DIMMs than
>to the individual chips on the DIMMs or soldered to a board.
>
>> > Memory, even just talking about main memory on the PC architecture, runs
>> > from 64 bits to 256 (possibly 512, if you count AMD's lightweight NUMA as
>> > parallel. Otherwise, 256 is for the quad-channel Xeon boards.)
>>
>> We were talking about memory, not processor implementation. Do you
>> have an example of an x86 processor with a wider than 64bit data path
>> to the DIMM (ignoring dual channel for the moment, which is simply
>> two DIMMs)?
>
>x86? No, although you're changing the goalposts, and I did say it was a
>quibble. The AMD dual channel implementation *IS* a full 128-bit path to
>memory, just split between two DIMMs.
>
>I have no idea what IBM uses for memory in their very high-end stuff, but
>that's not x86; even high-end stuff from Sun, etc, tends to just use
>multiple channels breaking down to DIMMs.
>
>> > ISTR some fairly ridiculous bus widths for high-end graphics cards, as well.
>>
>> We were... Do you really have parity/ECC on graphics cards?
>
>Not on consumer stuff.
>
Not running code, but pretty much only data, there really isn't much
*need* for ECC on graphics cards, as long as the error isn't obvious and
permanent. (There are tests for that.) Who cares all that much if a
pixel changes color slightly?

>It's been a *long* time since I've paid attention to high-end workstation
>graphics boards. It would be pretty implausible on consumer stuff or on
>today's "derived from consumer" FireGL or Quadro boards.
>
>Anyone have an old IBM PGA board from the mid-80s? I'd be quite surprised if
>that DIDN'T have parity.

--
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,-/-, __ __. ____ /_
(_/ / (_(_/|_/ / <_/ <_
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