What I've told you before (set forth below) speaks for itself. If you
use a k6+ or k6III CPU, the presence of 512k or 2M of motherboard
cache would be hardly noticeable except via benchmarks, regardless of
the amount of installed memory since the CPU will cache the entire
address space at full CPU speed. If you use a lesser CPU (k6-2 or
original k6 CPU) then you would likely see some noticeable differences
between 512k of onboard cache and 2M of mobo cache but only if the
entire memory space is not cached by the test setup. If you use more
memory than what the mobo can cache, then obviously, 2M of mobo cache
will be much better performance than 512k of mobo cache. The point is
there is more than 1 variable, mobo cache plus the amount of installed
memory must both be considered in comparing performance of such setups
where a lesser CPU is used.
My noting that motherboard cache and CPU selection are intertwined
(tho separate component subsystems) was only meant to highlight the
fact that selecting a cpu with full speed/full memory space expanded
caching capability renders the motherboard's caching limitations
nearly moot.
Tho the comments of the other post'er that you take exception with
were not perfectly stated, it is rather rude that you did not take the
comments as positive suggestions. This is not a forum for pedantic
tirades, but rather a place where many skilled people try to help
others in a polite fashion. It's too bad you can't take it all with a
grain of salt.
--
Best regards,
Kyle
"pigdos" wrote in message
| And your answer is "much too simply stated to be absolutely accurate
| information". Ever heard of the principle of locality? Are you
telling me
| that I'll see no difference between 2MB of on-board motherboard
cache vs.
| 512KB? The DFI K6bv3+ has 2MB of motherboard cache running at
100Mhz. The
| fact that it can cache more address space than 512KB would also make
a
| difference if I planned to use more memory right?
|
| --
| Doug
| "Kyle" wrote in message
|
| > "pigdos" wrote in message
| >
| > | Do you know what motherboard cache is?
| > | Do you realize it has nothing to do w/the CPU installed?
| >
| > Much too simply stated to be absolutely accurate information.
| >
| > This web page:
| > http://www3pub.amd.com/products/cpg/k6iii/trilevel.html
| > explains how the CPU onboard cache can have a major impact on
system
| > performance, even when a traditional mobo L2 cache is present.
| >
| > | I don't care if you've been installing computers for
| > | nine years
| > | or 20 years (I've been working with computers since 1987, I've
| > worked on the
| > | original IBM PC).
| >
| > Using a CPU such as a k6III or a k62+/3+ CPU makes a world of
| > difference, particularly since the onboard cache of these CPUs
runs at
| > full CPU speed, rather than at FSB speed, and will cache the
entire
| > addressable memory space of the processor. The motherboard L2
cache
| > becomes relegated to an "L3" role with these CPUs, and becomes
much
| > less important to overall performance due to its slower speed.
| >
| > | It's obvious you don't understand the difference between
| > | cache built into a motherboard (which was common 10 years ago)
and
| > that
| > | which resides in the CPU. I was never asking about how much RAM
the
| > CPU can
| > | cache.
| > |
| >
| > Now, if one installs more ram than the original mobo design will
| > cache, certain CPUs will still cache the "uncached" memory space
not
| > cached by the mobo cache. I don't really understand all this
| > squabble.
| >
| > It is well documented that once cache size exceeds 512k, only
marginal
| > performance gains will be realized in overall memory performance
| > (typical usage), even when more sophisticated 4-way associative
logic
| > is implemented. The tag ram limitations of the MVP3 chipset are
| > another issue well suited for a separate google search (a little
| > usenet searching will reveal all of the great posts on this
subject,
| > particularly how the mvp3 chipset designs typically do not cache
all
| > of 256 meg of memory in write-thru mode due to the 10 bit tag-ram
| > implementation).
| >
| > --
| > Best regards,
| > Kyle
| >
| >
|
| >> Stay informed about: DFI K6bv3+: maximum cacheable memory?