When will the Intel "real" quad-core processor come out?

* David Kanter:
> phuile wrote:
>> I've read threads here about both AMD and Intel bringing out new "real"
>> quad-core processors for 4+ socket servers in a few months.
>
> AMD won't have quad cores till the second half of this year AFAIK.
> Intel already offers quad Xeon DP systems.
>
>> I am
>> looking at a machine with 2 real quad Xeon processor. Does anyone know
>> approx. how long am I looking at - am I looking at March? June? Fall?
>> December? of 2007?
>
> How about they have been available since November?
>
> DK
>

OP If you mean single die - i.e. not two dual-cores put together - the
answer seems to be not until next year. Though as DK indicates, just
because the current ones are not single die, doesn't mean that they're
inferior.

--
Derek
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

Yes, I am talking about the "real" quad, not 2 dual core put together.
I am asking because I was in a discussion on another thread in this
forum and happened to read that some people are prepared to wait for
the "real" quad from Intel. The reason being that AMD will have them
coming "soon" and Intel shouldn't be far off if they want to compete. I
am just consdering whether I should wait or just go ahead with the
currently quad Xeon. That's why I am wondering whether anybody knows
about the time frame.
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

On Jan 22, 6:50 pm, "phuile" <phu... RemoveThis @yahoo.ca> wrote:
> Yes, I am talking about the "real" quad, not 2 dual core put together.]

Can you explain to me exactly what the difference is? It sure seems
like most software doesn't know the difference.

> I am asking because I was in a discussion on another thread in this
> forum and happened to read that some people are prepared to wait for
> the "real" quad from Intel.

Yes, well, some people also stored up tons of canned food for Y2K.
That just made them crazy...

> The reason being that AMD will have them
> coming "soon" and Intel shouldn't be far off if they want to compete.

What makes you think that Intel "needs" an integrated solution? The
only questions that a user should care about are:
1. What is the performance for the applications I care about, or
performance generally?
2. What is the power dissipation?
3. How much does it cost?

Having four cores on a single die is a way to improve performance.
However, it has drawbacks. You cannot bin the parts to match on
frequency and power dissipation. It is inherently more expensive to
produce, because larger dice have lower yields.

Using a multichip package has some advantages and disadvantages as
well. It is lower performance for multithreaded applications, but can
be higher performance for some single threaded applications, since the
frequencies will be higher. The reason that frequency will be higher
is that you can choose the two dice that go into the MCP, and pick so
that they are both really fast, or both slow. It's also probably 10x
cheaper to developer a new CPU with a multichip package than with a
new project.

Only zealots really want to portray it as a black and white issue.
AMD doesn't have the technology to do a multichip package so they have
been spending a lot of effort to get people to believe that "only
integrated quad cores are real quad cores", which is bunk. AMD's
performance will scale better because of the choices they made, but it
is balanced out by being somewhat more expensive in other ways.

If your workload isn't multithreaded, then it won't even matter
anyway.

> I am just consdering whether I should wait or just go ahead with the
> currently quad Xeon. That's why I am wondering whether anybody knows
> about the time frame.

Intel won't do four cores on a die for another 1.5-2 years. It really
depends on what your application is, most applications simply don't
have 4 threads, so you're better off buying the fastest dual core you
can get.

DK
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

On Jan 27, 10:06 pm, Yousuf Khan <bbb... RemoveThis @yahoo.com> wrote:
> phuile wrote:
> > Yes, I am talking about the "real" quad, not 2 dual core put together.
> > I am asking because I was in a discussion on another thread in this
> > forum and happened to read that some people are prepared to wait for
> > the "real" quad from Intel. The reason being that AMD will have them
> > coming "soon" and Intel shouldn't be far off if they want to compete. I
> > am just consdering whether I should wait or just go ahead with the
> > currently quad Xeon. That's why I am wondering whether anybody knows
> > about the time frame.Well, the answer seems to have been updated recently: not till sometime
> in 2008, _after_ Intel has converted to 45nm!
>
> http://www.tgdaily.com/2007/01/27/intel_45nm_penryn_details/
>
> For Intel with a shared L2 cache, it may not be as easy to redesign it
> to accommodate 4 cores rather than just 2.

Absolutely.

> AMD will only have a shared
> L3 cache, which is not as performance critical as an L2 cache, so some
> design flexibility might be available there.

This sentence really doesn't make much sense. How is there design
flexibility from having a shared L3 versus a shared L2 cache? It's
really all the same.

> As for the advantages of a real quad-core vs. dual-dual-cores, we really
> won't know the answer to that until AMD launches its real quad-core. So
> far people think it won't make a difference, but AMD is claiming that
> Barcelona will be upto 40% faster than Cloverton.

AMD is claiming that it will be 40% faster in SPECfp_rate than
EXISTING clovertown processors. Between now and then clovertown could
increase in clockspeed...imagine that. I bet on average the two
products will be about even, with AMD winning on FP and numerical
workloads, and Intel winning on more integer stuff.

> Pretty much what Intel
> claimed Conroe would be over Athlon 64 before it got launched; back then
> people were skeptical, but it turned out to be true. AMD might hold
> similar aces up its sleeve. We can assume that AMD will implement all of
> the same architectural improvements to its cores that Intel did to make
> Core 2 so good, so at the very least it will equal Core 2.

You could assume that, and you'd be wrong. AMD already stated that
they are not doing full LD/ST reordering, and they are only reordering
loads around other loads. That's much easier to do, and provides less
of a performance benefit.

Besides, any changes that AMD made to Barcelona were set in stone
around 1-2 years ago.

> Then AMD will
> have a shared L3 cache between the 4 cores, which should pool common
> data among all 4 cores rather than 2;

That's really easy to model though. The problem with Intel's quad
core is that there is duplication between the different L2 caches, but
it probably isn't that bad.

> the shared L2 cache worked wonders
> for Core 2 over Athlon 64, it was probably worth over 50% of the overall
> improvement by itself.

Can you back that statement up by data? Those numbers seem
ridiculously high.

DK
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

This message is not archived
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

phuile wrote:
> Yes, I am talking about the "real" quad, not 2 dual core put together.
> I am asking because I was in a discussion on another thread in this
> forum and happened to read that some people are prepared to wait for
> the "real" quad from Intel. The reason being that AMD will have them
> coming "soon" and Intel shouldn't be far off if they want to compete. I
> am just consdering whether I should wait or just go ahead with the
> currently quad Xeon. That's why I am wondering whether anybody knows
> about the time frame.

Well, the answer seems to have been updated recently: not till sometime
in 2008, _after_ Intel has converted to 45nm!

http://www.tgdaily.com/2007/01/27/intel_45nm_penryn_details/

For Intel with a shared L2 cache, it may not be as easy to redesign it
to accommodate 4 cores rather than just 2. AMD will only have a shared
L3 cache, which is not as performance critical as an L2 cache, so some
design flexibility might be available there.

As for the advantages of a real quad-core vs. dual-dual-cores, we really
won't know the answer to that until AMD launches its real quad-core. So
far people think it won't make a difference, but AMD is claiming that
Barcelona will be upto 40% faster than Cloverton. Pretty much what Intel
claimed Conroe would be over Athlon 64 before it got launched; back then
people were skeptical, but it turned out to be true. AMD might hold
similar aces up its sleeve. We can assume that AMD will implement all of
the same architectural improvements to its cores that Intel did to make
Core 2 so good, so at the very least it will equal Core 2. Then AMD will
have a shared L3 cache between the 4 cores, which should pool common
data among all 4 cores rather than 2; the shared L2 cache worked wonders
for Core 2 over Athlon 64, it was probably worth over 50% of the overall
improvement by itself. Also although Core 2 is a superb computational
engine, it's definitely not state-of-the-art at I/O throughput (i.e.
Hypertransport vs. front-side-bus). It's masking its I/O deficiencies
with big caches at the moment. The I/O throughput equation also includes
communications between processors in a multiprocessor system. When they
scale up over two processors, the FSB is a bottleneck.

Yousuf Khan

--
There is no failure, only delayed success
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

On Jan 27, 11:51 pm, The Kat <n... DeleteThis @katxyzkave.net> wrote:
> On 27 Jan 2007 22:59:14 -0800, "David Kanter" <dkan... DeleteThis @gmail.com> wrote:
>
>
>
> >On Jan 22, 6:50 pm, "phuile" <phu... DeleteThis @yahoo.ca> wrote:
> >> Yes, I am talking about the "real" quad, not 2 dual core put together.]
>
> >Can you explain to me exactly what the difference is? It sure seems
> >like most software doesn't know the difference.

>I could see, in any case when the same data was being processed
> by multiple cores, that there would be a benefit to a shared cache.
> But that's NOT what most quad-core chips will be doing, I think.

Yup. It becomes an issue when you have one CPU in the package trying
to write, while the other CPU is trying to read or write.

It's not ideal, but it is a lot cheaper and easier to do, and I think
both Intel and AMD make the appropriate choices for their respective
situations.

DK
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

David Kanter wrote:
>> For Intel with a shared L2 cache, it may not be as easy to redesign it
>> to accommodate 4 cores rather than just 2.
>
> Absolutely.
>
>> AMD will only have a shared
>> L3 cache, which is not as performance critical as an L2 cache, so some
>> design flexibility might be available there.
>
> This sentence really doesn't make much sense. How is there design
> flexibility from having a shared L3 versus a shared L2 cache? It's
> really all the same.


L3 doesn't need to have as low latency as lower-level caches. It's also
probably not as heavily accessed as the lower-level caches. Since 4
cores accessing the same memory would require more traffic management,
which adds latency, the fact that the cores are relying much less on the
L3 than L2 will result in less weighted-average latency increase.

In fact, L3 might be ideal for the experimental caches like AMD's ZRAM,
or Intel's FB-RAM. Neither of those have the low-latency of SRAM, but
SRAM's latency increases the larger and larger it gets, so at
sufficiently large enough sizes, the two technologies' latencies might
equal out. Intel is talking about a 16MB SRAM L3 cache in some future
quad-core processor (assume Nehalem), at 45nm. If ZRAM comes online for
AMD soon enough, then a 16MB ZRAM L3 can be substituted for a 2MB SRAM
L3, without much increase in real-estate.

Yousuf Khan
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

David Kanter wrote:
>
> On Jan 27, 11:51 pm, The Kat <n....RemoveThis@katxyzkave.net> wrote:
>> On 27 Jan 2007 22:59:14 -0800, "David Kanter" <dkan....RemoveThis@gmail.com> wrote:
>> I could see, in any case when the same data was being processed
>> by multiple cores, that there would be a benefit to a shared cache.
>> But that's NOT what most quad-core chips will be doing, I think.
>
> Yup. It becomes an issue when you have one CPU in the package trying
> to write, while the other CPU is trying to read or write.
>
> It's not ideal, but it is a lot cheaper and easier to do, and I think
> both Intel and AMD make the appropriate choices for their respective
> situations.


In Intel's case, the main advantage of the shared L2 is not so much that
the shared cache allows two cores to share each other's data, but
that it allows them the flexibility to allow a single core to take over
the whole L2 cache for itself on an as-needed basis. This gives a large
advantage in single-threaded performance. I don't think data sharing
between cores is that much of a big deal yet for anybody.

AMD's shared L3 cache may not be able to act in the same way as Intel's
shared L2 to increase single-thread performance, since it will likely be
a slower path to the core. However, the shared L3 will likely reduce
cache-coherency inter-processor traffic, as cores will search their own
L3 first before sending out a message to another processor over the HT
link. This is good for server applications, if not so much for PC
applications.

Yousuf Khan
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

David Kanter wrote:
>>AMD will only have a shared
>>L3 cache, which is not as performance critical as an L2 cache, so some
>>design flexibility might be available there.
>
> This sentence really doesn't make much sense. How is there design
> flexibility from having a shared L3 versus a shared L2 cache? It's
> really all the same.

But L3 can be:
a) slower (latency wise)
b) concurrency is less (L1/L2 handles much more traffic that just L1)

IOW -- it's easier to share slower L3 than faster L2.


>>Pretty much what Intel
>>claimed Conroe would be over Athlon 64 before it got launched; back then
>>people were skeptical, but it turned out to be true. AMD might hold
>>similar aces up its sleeve. We can assume that AMD will implement all of
>>the same architectural improvements to its cores that Intel did to make
>>Core 2 so good, so at the very least it will equal Core 2.
>
>
> You could assume that, and you'd be wrong. AMD already stated that
> they are not doing full LD/ST reordering, and they are only reordering
> loads around other loads. That's much easier to do, and provides less
> of a performance benefit.

But up to now AMD does virtually none of that while Intel did that stuff
(LD/LD) since P6. So finally AMD picks that long hanging fruit with
performance improvement associated with that. This sole thing should bring
performance up by 2 speedgrades.


> Besides, any changes that AMD made to Barcelona were set in stone
> around 1-2 years ago.
>
>>Then AMD will
>>have a shared L3 cache between the 4 cores, which should pool common
>>data among all 4 cores rather than 2;
>
> That's really easy to model though. The problem with Intel's quad
> core is that there is duplication between the different L2 caches, but
> it probably isn't that bad.

The problem is bus load. Coherency traffic is exposed on CPU's FSB and
occurs at FSB speed.


rgds
--
Sebastian Kaliszewski
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

On Jan 29, 7:42 am, Yousuf Khan <bbb... DeleteThis @yahoo.com> wrote:
> David Kanter wrote:
>
> > On Jan 27, 11:51 pm, The Kat <n... DeleteThis @katxyzkave.net> wrote:
> >> On 27 Jan 2007 22:59:14 -0800, "David Kanter" <dkan... DeleteThis @gmail.com> wrote:
> >> I could see, in any case when the same data was being processed
> >> by multiple cores, that there would be a benefit to a shared cache.
> >> But that's NOT what most quad-core chips will be doing, I think.
>
> > Yup. It becomes an issue when you have one CPU in the package trying
> > to write, while the other CPU is trying to read or write.
>
> > It's not ideal, but it is a lot cheaper and easier to do, and I think
> > both Intel and AMD make the appropriate choices for their respective
> > situations.
>
> In Intel's case, the main advantage of the shared L2 is not so much that
> the shared cache allows two cores to share each other's data, but
> that it allows them the flexibility to allow a single core to take over
> the whole L2 cache for itself on an as-needed basis.

I think in the *real* world, that's less important. For single
threaded benchmarks, it is an advantage. But sharing your cache is a
huge advantage for stuff like specjbb, tpcc, or real world stuff where
you have data sharing between processors.

If you look at the time it takes to acquire a lock from another
processor across the FSB (or even HT) versus from a shared cache,
you're talking an order of magnitude or more quicker.

> This gives a large
> advantage in single-threaded performance. I don't think data sharing
> between cores is that much of a big deal yet for anybody.

Not really. There's quite a few people who think otherwise...

> AMD's shared L3 cache may not be able to act in the same way as Intel's
> shared L2 to increase single-thread performance

Sure it will. It will decrease HT/memory accesses. That's a big win.

> , since it will likely be
> a slower path to the core. However, the shared L3 will likely reduce
> cache-coherency inter-processor traffic, as cores will search their own
> L3 first before sending out a message to another processor over the HT
> link. This is good for server applications, if not so much for PC
> applications.

I fail to see the distinction between the two situations (C2D and
Barcelona).

In each cache, the last level of on-die cache is shared between
multiple processors, providing a performance advantage (usually).

DK
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

On Jan 29, 7:17 am, Yousuf Khan <bbb....DeleteThis@yahoo.com> wrote:
> David Kanter wrote:
> >> For Intel with a shared L2 cache, it may not be as easy to redesign it
> >> to accommodate 4 cores rather than just 2.
>
> > Absolutely.
>
> >> AMD will only have a shared
> >> L3 cache, which is not as performance critical as an L2 cache, so some
> >> design flexibility might be available there.
>
> > This sentence really doesn't make much sense. How is there design
> > flexibility from having a shared L3 versus a shared L2 cache? It's
> > really all the same.
>
> L3 doesn't need to have as low latency as lower-level caches. It's also
> probably not as heavily accessed as the lower-level caches.

I think I need to be more clear. What do you mean by 'design
flexibility'? And what do you mean by less performance critical?

> Since 4
> cores accessing the same memory would require more traffic management,
> which adds latency, the fact that the cores are relying much less on the
> L3 than L2 will result in less weighted-average latency increase.
>
> In fact, L3 might be ideal for the experimental caches like AMD's ZRAM,
> or Intel's FB-RAM.

ZRAM was developed by ISi. What is FB-RAM? Is that Intel's version?

> Neither of those have the low-latency of SRAM, but
> SRAM's latency increases the larger and larger it gets, so at
> sufficiently large enough sizes, the two technologies' latencies might
> equal out.

There certainly will be a point where a denser cache is faster,
despite using 'slower' technology. It all really depends on your
interconnects.

> Intel is talking about a 16MB SRAM L3 cache in some future
> quad-core processor (assume Nehalem), at 45nm.

That's pretty reasonable. They already have a 16MB L3 for Tulsa.

> If ZRAM comes online for
> AMD soon enough, then a 16MB ZRAM L3 can be substituted for a 2MB SRAM
> L3, without much increase in real-estate.

Your numbers are a little off. The ZRAM folks claim that really at
best you can get a 5x improvement in density, not 8x. Secondly, I
have yet to see any actual proof of this, especially for high
performance caches. Thirdly, it's not clear how flexible AMD's L3
controller and interface is; there's a limit to how much it can
manage. Also, AMD would probably want to redo several aspects of the
uarch to support a larger L3 cache. I suspect that AMD might do some
inhouse trials of ZRAM using barcelona, but I think if they were going
to change, they'd do it during a die shrink or uarch change.

DK
 >> Stay informed about: When will the Intel "real" quad-core processor come out? 

David Kanter wrote:
> I fail to see the distinction between the two situations (C2D and
> Barcelona).
>
> In each cache, the last level of on-die cache is shared between
> multiple processors, providing a performance advantage (usually).
>

The disticntion is that Barcelona should do that at 4 core level and C2D at
2 core level.


rgds
\SK
 >> Stay informed about: When will the Intel "real" quad-core processor come out?